Field-Programmable Gate Arrays Engineer

Summary – Adaptive SoC FPGA Project (Freelance Contract)

• Start: ASAP
• Duration: 3–4 months (possible extension up to 6 months depending on scope)
• Role: FPGA / Digital Design Engineer

Project Overview:

Work on an Adaptive SoC FPGA system integrating both FPGA and ASIC components:

• One side: FPGA
• Other side: ASIC
• Both connected to a high-speed PHY interface

Responsibilities:

• Develop and program embedded software to configure the device, enabling workload-specific transactions between the two FPGAs.
• Implement low-level software on the SoC infrastructure FPGA to manage transaction flow between FPGA and ASIC.
• Perform digital design and FPGA development, ensuring correct connectivity and data traffic handling.

Work Setup:

• Mostly remote (no hard on-site dependencies).
• Initial 2–3 weeks on-site, then flexible remote schedule (ideally 2–3 days/week on-site if possible)