DFT Architect - Leuven, Belgium - Freelance

DFT Architect

Initial 6 month freelance contract + possible extensions

Leuven, Belgium (3 days onsite / week)

40 hours/week

ASAP start

Architect DFT solutions for SOCs with multiple sub-blocks-partitions and complex soft-hard IPs with complex DFT requirements Coordinate-Negotiate DFT requirements with the project teams and the customers.

The assignment

• Implement, and validate innovative DFT techniques on SOCs and sub-systems.
• Define timing constraints for DFT test-modes Insert boundary scan, compression, MBIST-R(epair), OPCG (OCC) for large-scale low-power designs in advanced nodes (7nm and beyond) Generate test patterns, debug-improve fault coverage, support debug of post-silicon test patterns, diagnose memory and scan issues.
• Work closely with the physical design team in the context of timing violations, signal-power integrity issues, routing congestion, etc.
• Work closely with the test engineering team on silicon characterization and validation

Required knowledge and skills

• 15+ years of experience in digital ASIC design, 10+ years of experience with DFT insertion and ATPG
• Basic fluency with Verilog or VHDL to write code for test logic when needed Experience as a DFT lead defining chip- and block-level DFT specifications in at least one project with hierarchical DFT
• Hands-on experience with defining SDC constraints for DFT, and inserting-verifying boundary scan, compression, MBIST & repair, OPCG or OCC, ATPG, fault coverage improvement, test debug, for large low-power designs in advanced nodes (7nm and beyond)
• Expert knowledge in IEEE 1149.1, 1149.6, and 1687 (IJTAG) standards and associated file formats (ICL, PDL)
• Preferably previous experience with defining a DFT flow Experienced in EDA tools such as Genus & Modus (Cadence), Tessent (Siemens), Synopsys toolset and simulation tools
• Experience using Tessent SSN is a plus
• Experienced in scripting languages especially TCL